1. Field of the Invention
The present invention relates to a Phase Lock Loop (PLL) frequency setting circuit used in a radio transceiver and the like.
2. Description of the Related Art
FIG. 2 is a schematic diagram of a conventional PLL circuit in a low-power radio transceiver.
The PLL circuit includes a Voltage Controlled Oscillator (VCO) 1 which generates a frequency Fout in a 400 MHz band, a frequency divider 2 which divides the frequency Fout and outputs a divided frequency Fdiv, a phase comparator 3 which compares phases of the divided frequency Fdiv and a reference frequency Fref and outputs a pulse of a width corresponding to a phase difference, an integrator 4 which integrates the pulse output from the phase comparator 3 and generates a control voltage for controlling the VCO 1, and a frequency setting circuit 5 for providing a frequency dividing value (i.e., a frequency set value) N to the frequency divider 2.
The frequency setting circuit 5 selects the frequency dividing value N for the frequency divider 2 on the basis of setting of basic frequencies A and B, switching of transmission and reception, and designation of a channel number and outputs the frequency dividing value N to the frequency divider 2. The frequency setting circuit 5 has four tables 5a, 5b, 5c, and 5d corresponding to combinations of a basic frequency and transmission and reception. The tables 5a to 5d are constituted by a memory such as a Read Only Memory (ROM). The tables 5a to 5d set a channel number CH as an address and store a frequency dividing value as data corresponding to the address. The channel number CH is given to address terminals AD of the tables 5a to 5d in common as an address signal from a channel setting unit 5e. Data output terminals DO of the tables 5a to 5d are connected to a selector 5f. A mode selection signal MOD designating a combination of the basic frequencies A and B and transmission and reception is provided to a control terminal of the selector 5f. The frequency dividing value N selected by the selector 5f based on the mode selection signal MOD is provided to the frequency divider 2.
FIG. 3 is a diagram showing an example of the tables 5a to 5d in FIG. 2.
For example, the table 5a is selected according to the mode selection signal MOD when the basic frequency A is set to perform transmission. When a channel number 1 is designated, a first address of the table 5a is read out and a 28-bit signal of 0x2d35228 (“0x” means that the following alphanumeric character is a hexadecimal number) is output as a frequency set value N.
However, the frequency setting circuit 5 in the PLL circuit needs a table for each combination of the basic frequencies A and B and transmission and reception. The respective data of the table has a 28-bit configuration. Thus, a large capacity memory is required.